1. Technical Field
The present invention relates to a built in self test system for a Programmable Logic Device (PLD). More particularly, the present invention relates to a BIST that detects faulty configuration memory cells and provides for debugging of various programming scenarios for configuration memory cells.
2. Related Art
Traditional PLDs such as Field Programmable Gate Arrays (FPGAs) and Complex PLDs (CPLDs) typically use millions of Static Random Access Memory (SRAM) cells forming a configuration memory to program the functionality of the implemented circuit. This programmability leads to many advantages such as ease of use, fast time-to-market, low non-recurrent engineering expenses, and on-chip design verification. With higher densities of configuration memory cells on PLDs, the configuration memory, however, is more prone to errors.
As transistor geometries become smaller and supply voltages become lower, on-chip memory cells are becoming more likely to be upset by collisions with cosmic particles, or single event upsets (SEUs). Having a greater number of configuration memory cells on a chip decreases the mean time to failure resulting from SEUs. The mean time to failure is further reduced with a higher cell density due to defects or faults in the memory cells themselves.
As PLD configuration memory density increases, it is further increasingly difficult to test for memory faults, or to account for the effect of SEUs. In particular, in order to test an IC programming, or configuration of the PLD a large number of test configurations may be required. The response to the test configurations is then monitored to determine if defects are present, or to determine the effect of SEUs. This testing is time-consuming and typically requires significant testing software provided external to the PLD.
For reference, a block diagram of components of one PLD, a conventional FPGA, is shown in FIG. 1. The FPGA includes input/output (IOBs) blocks 2 (each labeled 10) located around the perimeter of the FPGA, multi-gigabit transceivers (MGT) 4 interspersed with the I/O blocks 2, configurable logic blocks 6 (each labeled CLB) arranged in an array, block random access memory 8 (each labeled BRAM) interspersed with the CLBs, configuration logic 12, a configuration interface 14, an on-chip processor 16, and an internal configuration access port (ICAP) 15. The FPGA also includes a programmable interconnect structure (not shown) made up of traces that are programmably connectable between the CLBs 6 and IOBs 2 and BRAMs 8.
The configuration memory array 17 typically includes millions of the SRAM memory cells lying beneath the structure shown in FIG. 1. The configuration memory cells are programmed to configure the CLBs 6, IOBs 2, BRAMs 8 and appropriately connect the interconnect lines. The configuration memory array 17 can be visualized as a rectangular array of bits. The bits are grouped into frames that are one-bit wide words that extend in columns from the top of the array to the bottom. The configuration data values are typically loaded into the configuration memory array one frame at a time from the external store via the configuration interface 14.
In general, the FPGA of FIG. 1 is configured in response to a set of configuration data values that are loaded into a configuration memory array of the FPGA from an external store via configuration interface 14. Configuration interface 14 can be, for example, a parallel select map interface, a JTAG interface, or a master-serial interface. The configuration logic 12 provides circuitry for programming of the configuration memory array cells 17 typically at startup.
The FPGA can be reconfigured by rewriting data in the configuration memory array. In one reconfiguration method, the ICAP 15 is used to rewrite data in the configuration memory array in order to generate or instantiate the FPGA's internal logic (e.g., CLB's 6 and BRAMs 8). Without using the ICAP 15, reconfiguration can also be performed by loading reconfiguration frames through the configuration interface 14 using external customized logic components to over-write frame data in the configuration memory array.
It would be desirable to use the structure of an PLD to provide a less time consuming method for testing the functionality of high density configuration memory. In particular, it would be desirable to test a configuration memory without requiring programming to configure the PLD a number of times.